Support Microsoft Windows 98SE/ME, 2000, XP, and Vista Ĥ8-pin LQFP (Body Size: 7×7 mm) 48-pin QFN (Body Size: 6×6 mm, 0.Standard downstream port status indicators (Green and Amber LED control for each downstream port).Removable or Non-Removable Downstream Devices configuration.Global or Individual Over-Current Detection Mode select.System Requirements: Windows XP / Vista / 7 / 8 / 8.1 / 10. Ganged or Individual Power Control Mode select The USB cable can be easily unplugged, making travel easier and allows to use it with other USB devices.Automatic re-enumeration when Self-Powered switching to Bus-Powered.Automatic self-power status monitoring.Each TT could handle 64 periodic Start-Split transactions, 32 periodic Complete-Split transactions, and 6 none-periodic transactions.Alternate Interface 0 for Single-TT, and.Integrated 12MHz-to-480MHz Phase Lock Loop (PLL).Integrated 12MHz Oscillator with feedback resister, and crystal load capacitance.Integrated 5V to 3.3V and 1.8V regulator.
Usb 20 hub serial#
Most part of the chip will not be clocked unless needed. Low power consumption is achieved by using 0.18μm technology and comprehensive power/clock control mechanism. Special Build-In-Self-Test mode is designed to exercise all high, full, and low speed analog components on the packaging and testing stage as well. To guarantee high quality, the whole chip is covered by Test Scan Chain – include even the high speed (480MHz) modules, so that all the logic components could be fully tested before shipping. The whole design is based on state-machine-control to reduce the response delay time no micro controller is used in this chip. Six, instead of two, non-periodic transaction buffers are used to minimize potential traffic jamming. It adopts Multiple Transaction Translator (MTT) architecture to explore the maximum possible throughput.
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